1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit and, more particularly, a method of designing a semiconductor integrated circuit capable of suppressing a power supply noise generated in a power supply wiring.
2. Description of the Related Art
In recent semiconductor integrated circuits, a fluctuation in potential of the power supply becomes very wide because circuit elements in excess of 10million transistors are incorporated. In order to suppress such fluctuation in the potential of power supply, it is employed as the normal technology to provide the capacitor that is called the decoupling capacitor provided between the power supply and the ground.
In the prior art, in JP-A-2000-277618, as the method of reducing the power supply noise, the method of calculating a capacitance value used to reduce the power supply noise every logic cell (every combinational logic circuit in which the transistors as the circuit elements of the semiconductor integrated circuit are combined to be contained within a uniform width) and then arranging a power-supply capacitor cell 12 with an appropriate capacitance value besides a logic cell (logic gate cell) 11 respectively, as shown in FIGS. 18(a) and (b), has been proposed. Here, 13, 14 denote a load capacitance of the logic gate cell 11 respectively, and 15 denotes a power-supply capacitance of the power-supply capacitor cell.
Also, in Non-Patent Literature 1, the method of executing the optimization based on the voltage drop information and the consumption current information derived from the placement/routing information of the semiconductor integrated circuit has been proposed.
However, the method set forth in JP-A-2000-277618 is not practical because it is impossible to sufficiently ensure a required capacitance (decoupling capacitance) within a limited chip area. Also, in some cases the unnecessary capacitor cell must be placed because the transistor acts as the capacitance in its inoperative status. In such case, sometimes the resultant placement is far from an ideal model.
Also, in the method set forth in Proceedings of ASP-DAC2004 pp. 505-6B-2: A Fast Decoupling Capacitor Budgeting Algorithm for Robust On-Chip Power Delivery, the appropriate placement of the decoupling capacitor cannot be realized because a capacitive effect of the inoperative transistor is not taken into consideration. Also, the layout must be designed previously, and thus the steps required until the layout is completed consume much time.
In this manner, as the approach of suppressing a dynamic voltage fluctuation such as the power supply noise, or the like, the approach of inserting the capacitor between the power supply and the ground, inserting the inductance into the power supply wiring or the ground wiring, or the like is employed. However, there exist the problems such that the approach of inserting the capacitor has the great areal demerit because the capacitor is formed uniformly in all cells, and also takes a much processing time because the power supply network must be dynamically analyzed in advance, and the like.